.SUBCKT ECF20N20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | \|| [9] * |-||--| >|O---O-----| * | | /|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z / \D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.362 LAMBDA=0.06 KP=3.097 RS 8 3 0.178 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.77e-9 VJ=0.1 M=0.28 RDS 8 9 1e+06 RD 9 1 0.265 RG 2 7 42 * Gate Source capacitance Cgs0 CAP1 7 8 900e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 18.7e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=75e-12 VJ=0.1 M=0.768 ************************* .ENDS ECF20N20